Field of the Invention
The present invention is directed in general to data processing systems. In one aspect, the present invention relates to clock distribution to multiple lanes on an integrated circuit chip.
Description of the Related Art
A data processing system may require multiple clock signals for certain applications. Typically, a plurality of clock drivers are distributed along a clocking path to drive all the clock signal loads along the clocking path, especially in high clock frequency applications such as serializer/deserializer (SerDes) clocking scheme. Such clock drivers may employ phase-locked loops (PLLs) to generate the clock signals in phase with the phase of a master or reference clock signal, but when inductive clock drivers are operating at the same frequency or harmonically related frequencies, there is a significant risk of injection locking problems arising due to electric and magnetic couplings between inductive components causing serious interference between clock nets. Injection locking may pull the PLL output clock signals out of phase with their respective reference clock signals and/or result in duty cycle distortions on the local clock signal. This conflict between the inherent operation of the PLLs and injection locking can result in the PLLs generating clock signals with an unacceptable level of jitter. Existing solutions for controlling injection locking effects employ dedicated circuitry for detecting and correcting operations at the cost of higher circuit complexity and power consumptions. Other solutions attempt to isolate the PLLs to reduce the coupling between the PLLs to an insignificant level, but such PLL isolation techniques have limited effectiveness as PLLs increasingly operate at high frequencies (resulting in higher sensitivity to jitter) and/or as device dimensions shrink (resulting in reduced isolation effectiveness as the distance between PLLs is reduced). As a result, the existing solutions for protecting against injection locking are extremely difficult at a practical level.